Senior Engineer - Physical design
Core
Senior Physical Design Engineer responsible for RTL-to-GDS implementation, timing closure, and signoff checks for Arm SoCs and cores.
Role type
Senior IC physical design engineer (ASIC)
Builds
Arm cores, systems, and System-on-Chips (SoCs)
Domain
Semiconductor / ASIC Physical Design
Required skills
ASIC implementation flow (RTL to GDS), Synthesis, Timing Closure, Timing Constraints, Tape-out experience (multi-million gate), LEC/CLP/ECO implementation, Python scripting
Preferred skills
Low power design techniques (power gating, voltage/frequency scaling), Verilog RTL design, DFT modes understanding, Tcl/Shell/Perl scripting (via careerplan.io/jobs/100024340160-senior-engineer-physical-design-at-arm)
Technologies
Python, Tcl, Shell, Perl, LEC, CLP, ECO
Responsibilities
Lead synthesis and constraints development; Analyze design timing, area, and power; Develop and deploy new methodologies to improve implementation efficiency; Support detailed implementation analysis and data-mining; Work with implementation and physical IP RTL design teams to drive optimization.
Seniority
Senior, hands-on IC
