Senior Implementation Engineer
Core
Lead full-chip and hierarchical SoC physical design from netlist to GDSII, driving closure across timing, power, and verification.
Role type
Senior IC ASIC Physical Design Engineer
Builds
Advanced process node chips (5nm/3nm/2nm)
Domain
Semiconductor / VLSI Design
Required skills
hierarchical floor planning, partitioning strategy, pin/IO/bump planning, power planning, full-chip CTS, physical verification (DRC/LVS/ERC), IR/EM/noise analysis, ESD planning, EDA tool expertise (Innovus, ICC2, Fusion Compiler, Tempus, PrimeTime, Calibre), advanced node experience
Preferred skills
tape-out leadership, packaging co-design, scripting automation (Python/TCL/SKILL)
Technologies
Innovus, ICC2, Fusion Compiler, Tempus, PrimeTime, Calibre, Python, TCL, SKILL
Responsibilities
Lead chip-level hierarchical floor planning and block-level integration; Drive partitioning strategy and hierarchical design implementation; Own pin, IO, and bump planning/routing; Define and execute power planning; Perform and manage full-chip CTS and clock architecture optimization; Lead chip integration across blocks; Execute physical verification sign-off; Drive full-chip closure including congestion, IR/EM, timing, and noise analysis; Support tape-out activities; Mentor junior engineers (via careerplan.io/jobs/100792411840-senior-implementation-engineer-at-arm)
Seniority
Senior, hands-on IC
