Semiconductor Packaging Research Engineer
Core
Drives technology research for advanced packaging and heterogeneous integration, evaluating new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs.
Role type
Semiconductor Packaging Research Engineer
Builds
Future product platforms via advanced packaging concepts and integration flows
Domain
Semiconductor manufacturing / Advanced packaging / Heterogeneous integration
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor packaging research, process integration, modeling/simulation, reliability assessment, DOE execution, defect/yield learning, multi-physics simulation, advanced packaging technologies (flip chip, chiplets, 2.5D/3DIC, hybrid bonding, interposers, HBM integration)
Preferred skills
Prototype builds, technology readiness assessment, research-to-development transfer, package-system co-optimization, chip-package-board co-design
Technologies
ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP
Responsibilities
Research advanced packaging concepts; define integration flows and research vehicles; develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models; translate product needs into research hypotheses and technical plans; document outputs through reports, design guidance, IP, and publications; collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams
Seniority
Mid-level IC (1+ years experience)