Senior Design Engineer
Core
Develop Arm custom standard cells for advanced sub-3nm process technologies and co-optimize cell architectures to improve power, performance, and area (PPA) of SoCs.
Role type
Senior IC physical design engineer (standard cell design)
Builds
High-performance, low-power logic libraries for next-generation SoCs and custom digital IP
Domain
Semiconductor / Advanced Process Nodes (sub-3nm)
Required skills
Transistor-level circuit design, Standard cell characterization, MOSFET device physics, Static CMOS design, EDA view generation, SPICE simulation, Python/Perl scripting, Layout effects analysis, Process variability modeling
Preferred skills
Physical design implementation flows (place-and-route), Advanced-node design considerations, Automation development for design flows (via careerplan.io/jobs/100290470976-senior-design-engineer-at-arm)
Technologies
SPICE, Python, Perl, EDA tools
Responsibilities
Develop and optimize Arm custom standard cells for advanced sub-3nm process technology nodes; Perform standard cell characterization, modeling, and EDA view generation; Design, analyze, and verify transistor-level circuits to meet PPA and reliability requirements; Co-optimize circuit designs with physical design engineers; Collaborate with mask design engineers to optimize cell layouts; Develop and execute robust QA and validation methodologies; Identify opportunities to improve characterization methodologies and automation; Analyze complex technical issues and develop practical solutions.
Seniority
Senior, hands-on IC
