Senior Engineer- Modelling
Core
Develop, validate, and deploy models for Physical IP (standard cells, embedded memories, custom blocks) to support SoC designers in building high-performance chips.
Role type
Senior IC modeling engineer (Physical IP)
Builds
Production-ready models for Physical IP
Domain
Semiconductor / ASIC Design / EDA
Deliverable
production ML models (via careerplan.io/jobs/100747323856-senior-engineer-modelling-at-arm)
Required skills
ASIC/SoC build flows, Verilog/SystemVerilog, Python/Tcl/Perl scripting, EDA tools (simulation/synthesis/DFT/ATPG), digital circuit fundamentals, model validation methodologies
Preferred skills
Memory BIST, ATPG, low-power design, AI/LLM for workflow automation, Git/Gerrit, CI/CD
Technologies
Python, Tcl, Shell, Perl, SystemVerilog, Verilog, EDA tools
Responsibilities
Coordinate with IP design teams and EDA vendors to set modeling requirements; Develop and validate models in EDA flows; Automate development and release workflows using scripting and AI tools; Investigate modeling issues and apply solutions.
Seniority
Senior, hands-on IC