Design Engineer
Core
Develop transistor-level physical layouts for Arm custom standard cells in sub-3nm process nodes to deliver high-performance, area-optimized logic libraries for next-generation SoCs and custom digital IPs.
Role type
Senior IC physical design engineer (standard cell layout)
Builds
Custom standard cell libraries for infrastructure, client, automotive, and IoT market segments (via careerplan.io/jobs/100290446080-design-engineer-at-arm)
Domain
Semiconductor manufacturing / VLSI / Custom IC design
Required skills
CMOS transistor-level circuit layout, Schematic interpretation, Stick-diagram development, Transistor placement and diffusion optimization, DRC and LVS, Physical-verification debugging, Design Rule Manual interpretation, Parasitic resistance and capacitance analysis, PPA-aware physical implementation, Semiconductor manufacturing fundamentals
Preferred skills
Physical design implementation flow experience, Experience with custom IC, standard-cell, memory, or analog layout
Technologies
Cadence Virtuoso, Synopsys Custom Compiler, Siemens Calibre, Python, Tcl, SKILL
Responsibilities
Independently develop transistor-level physical layouts from circuit schematics, Perform DRC, LVS and physical-verification debugging, Optimize device placement, diffusion sharing, routing and pin accessibility, Apply layout techniques to improve power, performance and area (PPA), Review straightforward layout work produced by other engineers, Support development of less-experienced engineers through knowledge sharing
Seniority
Senior, hands-on IC
