Mixed Signal Design Verification Engineer
Core
Functional verification of mixed signal logic components, including analog behavioral modeling, to ensure designs meet specification requirements.
Role type
Mixed Signal Design Verification Engineer
Builds
IP verification plans, test benches, verification environments, and system simulation models for power delivery technology.
Domain
Semiconductor / Mixed Signal IC Design
Required skills
Digital logic, VHDL/Verilog/System Verilog, Testbench component development (OVM/UVM), Design debugging, Analog behavioral modeling, Power and timing analysis, System simulation modeling
Preferred skills
Analog debug skills, Real number (current, voltage) simulation modeling and debug skills
Responsibilities
Develop IP verification plans, test benches, and verification environments; Execute verification plans and run system simulation models; Replicate, root cause, and debug issues in presilicon environments; Collaborate with digital and analog architects, RTL developers, and physical design teams; Document test plans and drive technical reviews; Maintain and improve functional verification infrastructure and methodology.
Seniority
Mid-Senior, hands-on IC (via careerplan.io/jobs/JR0285739-mixed-signal-design-verification-engineer-at-intel)
