Senior DFT Engineer
Core
Lead DFT verification and debug for mixed-signal IP blocks (SERDES, Sensors, Non-volatile memory) within complex SoCs, driving pattern bring-up and stabilization on silicon. (via careerplan.io/jobs/99391140016-senior-dft-engineer-at-arm)
Role type
Senior DFT Engineer (Mixed Signal)
Builds
Production-ready mixed-signal IP blocks and SoC test infrastructure
Domain
Semiconductor / Mixed-Signal Design & Test
Required skills
Mixed-signal DFT verification, ATE pattern development & debug, JTAG/iJTAG architecture, Siemens Tessent tools, PDL development, SERDES loopback verification, BIST, Failure analysis
Preferred skills
SCAN & MBIST, Lane repair schemes, Test-time optimization
Technologies
Siemens Tessent, IEEE 1149.1, IEEE 1687, ATE, JTAG, iJTAG, SERDES, DDR PHY, PCIE, USB
Responsibilities
Perform DFT verification of mixed-signal IP blocks in complex SoC; Develop, verify, and debug ATE test patterns and drive pattern bring-up on silicon; Perform ATE pattern debug and stabilization; Develop and maintain PDL for embedded instruments and iJTAG networks; Debug complex pattern, timing, protocol, and DFT infrastructure issues; Collaborate with design, verification, and test engineering teams.
Seniority
Senior, hands-on IC
