DFT Implementation Engineer
Core
Develop logic and RTL coding to integrate Design for Test (DFT) features like SCAN, MBIST, and BSCAN into complex SoC and IP designs, ensuring high test coverage and manufacturing readiness.
Role type
Senior IC DFT Design Engineer
Builds
Industry-leading SoC and IP solutions with integrated DFT capabilities for Intel silicon products
Domain
Semiconductor design and manufacturing (ASIC/SoC)
Deliverable
production ML models | product features
Required skills
RTL design (Verilog, VHDL, SystemVerilog), ATPG, scan insertion, MBIST/repair, timing closure, test content generation, HVM content development, cross-functional collaboration
Preferred skills
Tessent Fast IO, ISTK, IEEE 1687/1149.1/1500/1838 standards, DFT tools (Siemens EDA, Synopsys, Cadence), scripting (TCL, Perl, Python), low-power design methodologies
Technologies
Verilog, VHDL, SystemVerilog, TCL, Perl, Python, Siemens EDA Tessent, Synopsys DFT Compiler, Cadence Modus, ATE
Responsibilities
Develop RTL and structural code for DFT functionality; provide timing closure support; optimize designs for power, performance, area, and test coverage; drive verification efforts; support IP and SoC integration; develop HVM content for ATE; collaborate with post-silicon teams to verify features on silicon
Seniority
Senior, hands-on IC
