Senior Engineer-DFT
Core
Design and verification of digital test structures for semiconductor chips, focusing on scan compression, memory BIST, logic BIST, and silicon debug.
Role type
Senior IC DFT Engineer
Builds
Testable silicon chips with embedded diagnostics and BIST solutions
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics, Verilog RTL, TCL, Perl, Unix/Linux environments
Preferred skills
IEEE 1149, 1500, 1687, 1838 standards, Synthesis & Static Timing Analysis, SoC style architectures (multi-clock domain, low power), Siemens DFT tools, Arm IP (Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug), 2.5D and 3D test, Siemens/Cadence/Synopsys DFT and simulation tools
Technologies
Verilog, TCL, Perl, Siemens, Cadence, Synopsys, Arm Cortex, Mali, AMBA, CoreLink, CoreSight
Responsibilities
Implement scan compression and insertion strategies, Develop memory and logic BIST schemes, Execute at-speed testing and fault simulation, Perform silicon debug and diagnostics, Write verification code in Verilog/TCL/Perl, Utilize DFT tools for back-annotated gate level verification
Seniority
Senior, hands-on IC