Lead SOC DFT Engineer
Core
Implementing and validating Design for Test (DFT) strategies to ensure the testability and quality of semiconductor designs throughout the product development cycle.
Role type
Senior SoC DFT Engineer
Builds
Robust and reliable semiconductor products
Domain
Semiconductor / Embedded Processing / Digital and Mixed Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT strategies, ATPG, scan insertion, test pattern generation, DFT EDA tools (Cadence Modus, Genus), scan compression, boundary scan, memory BIST, JTAG, IEEE 1149.1 standards, scripting (Perl/Python)
Preferred skills
Silicon bring-up, post-silicon debug
Technologies
Cadence Modus, Genus, Perl, Python
Responsibilities
Define testability requirements, implement DFT strategies, validate DFT implementation, collaborate with DFT engineering teams
Seniority
Senior, hands-on IC
