Static Timing Analysis Engineer
Core
Physical Design Timing Engineer ensuring optimal performance and efficiency for Intel's next-generation SoCs in high-performance computing and AI.
Role type
Senior IC physical design timing engineer
Builds
High-performance, low-power SoCs for Intel products
Domain
Semiconductor / Physical Design / Static Timing Analysis
Deliverable
production ML models | product features
Required skills
Static timing analysis, timing modeling, constraint generation, optimization techniques, PVT condition analysis, clock network design, power optimization, cross-functional collaboration
Preferred skills
SoC development, clocking design principles, high-performance computing, low-power design environments
Technologies
Static timing analysis tools
Responsibilities
Perform timing analysis and optimization at chip and block levels; Generate and verify timing constraints; Conduct timing rollups and develop power-optimized clock networks; Define methodologies for quality timing models; Set PVT conditions for timing analysis; Collaborate with architecture, clock, logic, and backend teams for clocking balance and partitioning
Seniority
Senior, hands-on IC
