Principal ASIC Design Engineer
Core
Principal ASIC Design Engineer owning RTL design, micro-architecture, and timing closure for high-speed interface digital blocks in a mixed-signal chip.
Role type
Principal ASIC Design Engineer (High-Speed Interface/PHY)
Builds
High-speed interface ASICs for memory and storage solutions
Domain
Semiconductor / Memory and Storage / High-Speed Interfaces
Required skills
SystemVerilog RTL design, Logic Synthesis, Static Timing Analysis, CDC analysis, RTL simulation and debug, Mixed-signal design interface, AI tools for productivity
Preferred skills
Place-and-route, Physical verification, Mixed-signal/PHY implementation, High-speed PHY architectures, DFT methodologies, Formal property verification
Technologies
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold, Cadence Innovus, Mentor Calibre
Responsibilities
Own micro-architecture and RTL implementation of digital soft IP blocks; Define block-level architecture specifications and interface control documents; Execute logic synthesis and drive optimization toward PPA targets; Develop and maintain SDC constraints and close static timing analysis; Serve as primary digital interface to layout and implementation teams; Self-verify RTL through simulation and waveform debug.
Seniority
Principal, hands-on IC (via careerplan.io/jobs/44634961-principal-asic-design-engineer-at-micron)
