Principal Design Engineer – High-Speed Interconnect
Core
Design and integrate high-speed interconnect subsystems (PCIe, CXL, UALink) for silicon products, translating system requirements into microarchitecture and RTL.
Role type
Principal Design Engineer (High-Speed Interconnect)
Builds
High-performance digital subsystems and silicon products
Domain
Semiconductor / High-Speed Interconnects
Deliverable
production ML models | product features | infrastructure
Required skills
SystemVerilog, microarchitecture design, PCIe/CXL/UALink protocols, cache hierarchies, AXI/CHI/ACE interfaces, CDC/RDC/reset sequencing, formal verification, timing analysis, RTL synthesis
Preferred skills
PCIe Gen6+, CXL 2.0+, chiplets, RAS/IDE/TDISP, third-party IP integration
Technologies
SystemVerilog, PCIe, CXL, UALink, AXI, CHI, ACE, APB, Synopsys/Cadence tools (implied by synthesis/timing)
Responsibilities
Own microarchitecture and RTL development for interconnect subsystems; drive development from concept to delivery; analyze traffic patterns to guide implementation tradeoffs; lead technical reviews and debug cross-functional issues; mentor engineers
Seniority
Principal, hands-on IC with technical leadership