Senior/Staff Analog Design Engineer - SerDes
Core
Design high-speed SerDes and mixed-signal subsystems for next-generation SoCs, spanning circuit implementation through post-silicon validation.
Role type
Senior/Staff Analog Design Engineer (SerDes)
Builds
High-speed SerDes blocks (serializers, TX drivers, TIAs, CTLEs, CDRs, deserializers, clock generation) in advanced FinFET nodes
Domain
Semiconductor IC design, high-speed signaling, mixed-signal systems
Deliverable
production ML models | product features
Required skills
Analog/mixed-signal IC design, SerDes design (25 Gbps+), high-speed signaling concepts, advanced FinFET node expertise, EM simulation, Verilog-A modeling, post-silicon bring-up
Preferred skills
None stated
Technologies
Cadence Virtuoso, Spectre
Responsibilities
Architect and design high-speed SerDes blocks from specification through silicon; Perform schematic and post-layout simulations (EM-IR, reliability); Run EM simulations for passives and on-die routing; Develop behavioral and Verilog-A models; Supervise mask designers; Collaborate on interfaces and link-level performance; Support post-silicon bring-up and debug
Seniority
Senior/Staff, hands-on IC design