Senior layout Engineer – DPG Layout
Core
Implement design and physical implementation of analog, mixed-signal, and custom digital blocks for full-chip integration in advanced CMOS processes.
Role type
Senior IC layout engineer (analog/mixed-signal)
Builds
Analog and mixed-signal blocks (sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps) for memory and storage solutions
Domain
Semiconductor manufacturing / Analog IC design
Required skills
Analog layout fundamentals, Cadence Virtuoso (VLE/VXL), Calibre DRC/LVS, AI-driven automation (SKILL/Python/TCL), electromigration/latch-up/IR-drop/crosstalk analysis, design constraint interpretation
Preferred skills
Memory layout environments (DRAM, SRAM, CAM, OTP), ECO and integration-level updates (via careerplan.io/jobs/43133678-senior-layout-engineer-dpg-layout-at-micron)
Technologies
Cadence Virtuoso, Calibre, SKILL, Python, TCL
Responsibilities
Own block-level layout execution with focus on quality and turnaround time; Perform layout verification (DRC, LVS, Antenna, Yield); Use AI tools to automate repetitive tasks; Collaborate with Design, Verification, and CAD teams; Assist in reviewing sub-block layouts from junior engineers
Seniority
Senior, hands-on IC
