Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon
Core
Senior IC Layout Engineer responsible for high-speed analog and mixed-signal blocks (EICs) and photonic ICs (PICs) for optical interconnects in AI data centers.
Role type
Senior IC Layout Engineer (Silicon Photonics & Mixed-Signal)
Builds
High-speed analog/mixed-signal ICs, photonic ICs, and integrated EIC-PIC solutions for AI clusters.
Domain
Semiconductor, Silicon Photonics, AI Data Center Infrastructure
Deliverable
production ML models | product features
Required skills
Custom analog/RF/high-speed mixed-signal IC layout, Cadence Virtuoso (Layout XL), parasitic-aware design, electromigration/IR drop closure, physical verification (DRC/LVS), electromagnetics fundamentals, PDK integration
Preferred skills
SiGe BiCMOS layout, FinFET CMOS layout (7nm+), photonic IC layout (waveguides, curvilinear geometry), scripting (SKILL/Python), 2.5D/3D integration, optical front-end layout
Technologies
Cadence Virtuoso, Calibre/PVS, QRC/StarRC, SKILL, Python, gdsfactory, KLayout, IPKISS
Responsibilities
Own floorplan and layout for high-speed analog/mixed-signal blocks; execute device-level matching and symmetry; route high-speed signal paths with impedance control; drive parasitic-aware layout and sign-off; support PIC layout and build photonic PCell libraries; own EIC-PIC integration and layout standards.
Seniority
Senior, hands-on IC