IC Layout Engineer – Optical Engine Silicon
Core
Own layout for high-speed analog and mixed-signal ICs (EICs) and support photonic IC (PIC) layout for optical interconnects in AI data centers.
Role type
IC Layout Engineer (Analog/Mixed-Signal with Photonic support)
Builds
Electronic ICs (EICs) and Photonic ICs (PICs) for AI clusters
Domain
Semiconductor / Silicon Photonics / AI Infrastructure
Deliverable
production ML models | product features
Required skills
Custom analog/mixed-signal IC layout, Cadence Virtuoso (Layout XL), Parasitic-aware layout, DRC/LVS/Extraction, Electromigration/IR drop analysis, High-speed signal routing, Scripting (SKILL/Python)
Preferred skills
SiGe BiCMOS layout, Advanced FinFET CMOS (7nm+), Photonic IC layout (waveguides, curvilinear), Parametric photonic cells (PCells), 2.5D/3D integration, Optical front-end blocks (TIA, modulators)
Technologies
Cadence Virtuoso, Calibre, PVS, QRC, StarRC, gdsfactory, KLayout, IPKISS
Responsibilities
Device placement, matching, symmetry, shielding, guard rings, and routing from floorplan to sign-off; Execute parasitic-aware layout and extraction; Route high-speed signal paths with impedance and return path control; Run DRC, LVS, antenna, and density checks; Support tape-out and chip finishing; Build layout automation scripts
Seniority
Mid-level IC Engineer (1-3 years experience)