Senior Layout Engineer
Core
Develop custom standard cell layouts for Arm's next-generation SoCs and digital IPs in sub-3nm process nodes, optimizing for performance, area, and power.
Role type
Senior IC physical design engineer (standard cell layout)
Builds
High-performance, DRC-clean logic libraries for infrastructure, automotive, and IoT markets
Domain
Semiconductor / Deep submicron circuit design
Required skills
Standard cell layout design, Physical verification (DRC/LVS), Automation scripting (Python/SKILL/TCL), Advanced node technology (5nm/3nm/2nm), PPA optimization, Cell abutment and profiling, LEF/GDS view management
Preferred skills
Physical design implementation flow, AI tools for productivity
Technologies
Cadence Virtuoso, Calibre, Python, SKILL, TCL, PERL, LEF, GDS
Responsibilities
Design logic standard cells optimized for PPA; Collaborate with circuit designers to translate schematics into layouts; Drive DRC and LVS closure using verification tools; Perform layout debugging and root-cause analysis; Handle cell abutment, profiling, and integration constraints; Automate layout QA and regression checks; Review physical views for digital flows. (via careerplan.io/jobs/99522005200-senior-layout-engineer-at-arm)
Seniority
Senior, hands-on IC