Senior Analog Layout Designer
Core
Create layouts for RX/TX lane macros and support lane-level integration for high-performance decode accelerators.
Role type
Senior Analog Layout Designer
Builds
RX/TX lane macros and integrated analog blocks for rack-scale decode accelerators
Domain
Semiconductor hardware design, advanced process nodes (2nm-5nm)
Deliverable
production ML models | product features
Required skills
Analog Layout Design, TSMC FinFET process knowledge (2nm, 3nm, 4nm, 5nm), block/macro floor-planning, block integration, routing, clock distribution, power grid implementation, device matching, symmetry, parasitic reduction, noise isolation, LVS/ERC/DRC/Density/DFM/Antenna verification, EM/IR analysis, ESD/Clamps layout, layout effects (LOD/OSE/PSE/WPE/MBE/LDE), lane integration, revision-controlled design libraries
Preferred skills
SKILL, TCL, Python scripting
Technologies
Cadence Virtuoso, Calibre, Pegasus
Responsibilities
Design layouts for RX/TX lane macros, perform block integration and routing, run and debug verification flows (LVS/ERC/DRC), conduct EM/IR analysis, manage tape-out verifications
Seniority
Senior, hands-on IC
