Principal Hardware Engineer - 3rd Party IP Engineer
Core
Principal Hardware Engineer managing 3rd party IP integration for DDR/LPDDR/GDDR/HBM/eMMC memory interface cores in SoC development.
Role type
Principal Hardware Engineer (3rd Party IP Integration)
Builds
Memory interface cores for AI, hyper-scaler, communications, and storage applications.
Domain
Semiconductor / SoC Design / Memory Interfaces
Required skills
DDR interface expertise (DDR, LPDDR, GDDR, HBM, eMMC), SoC PHY integration, timing analysis, packaging, multi-chip integrated packaging, project management for 3rd party developers, ASIC design flows (logic synthesis, physical design, timing, DRC/LVS, formal verification), Design-For-Test (DFT) concepts, post-silicon validation.
Responsibilities
Define core requirements, validate IP developer competence, oversee core development and technology compliance, manage 3rd party developers, advise design center on core integration, develop statements of work, lead provider progress reviews, drive problem resolution using reporting tools, assist with 8D follow-through for supplier issues.
Seniority
Principal, hands-on IC with strategic oversight
