Staff Post-Silicon DDR Characterization Engineer
Core
Validate and characterize next-generation Arm SoCs, focusing on DDR/LPDDR memory subsystems across PVTF conditions to ensure power, performance, stability, and reliability.
Role type
Staff Post-Silicon DDR Characterization Engineer
Builds
Next-generation Arm System-on-Chip (SoC) memory subsystems
Domain
Semiconductor / High-Speed Memory Interfaces
Required skills
Post-silicon DDR/LPDDR characterization, silicon debug, root-cause analysis, Mixed Signal Oscilloscope (MSO) operation, eye margining, voltage/frequency shmoo testing, Python/C++ automation, PVTF analysis
Preferred skills
HBM/PoP/on-package memory characterization, signal integrity analysis, memory bandwidth/latency profiling, Arm SoC architecture knowledge, automated characterization framework development
Technologies
DDR4/DDR5/DDR6, LPDDR4/4X/LPDDR5/5X, MSOs, Logic Analyzers, Python, C/C++, Arm Assembly
Responsibilities
Define and execute DDR/LPDDR post-silicon characterization plans; Identify, reproduce, and debug complex silicon and memory subsystem issues; Perform eye margining, timing analysis, and electrical measurements; Analyze controller/PHY/system-level behavior to identify bottlenecks; Develop reusable automation for characterization and data collection; Provide technical leadership and mentor engineers
Seniority
Staff, hands-on IC with technical leadership