Principal TPIP/HSIO Engineer
Core
Principal Quality Engineer ensuring pre-silicon quality of high-speed I/O (HSIO) subsystems including DDR, PCIe, and eUSB through simulation, correlation, and vendor partnership.
Role type
Principal TPIP/HSIO Quality Engineer
Builds
High-speed I/O blocks (DDR, PCIe, eUSB, D2D) for System-on-Chip (SoC) integration
Domain
Semiconductor / High-Speed Interface Design
Required skills
High-speed interface design, validation, or bring-up (DDR, PCIe, SerDes), Post-silicon characterization (BER, margining), Pre-silicon simulation correlation, Scripting (Python, TCL), DFX metrics analysis
Preferred skills
TPIP Council leadership, Cross-functional team collaboration
Technologies
DDR, PCIe, eUSB, SerDes, Python, TCL
Responsibilities
Collaborate with IP vendors and integration teams to achieve high silicon quality performance; Drive closure on DFX metrics (test coverage, margin analysis, stuck-at/scan coverage, clock-domain checks); Develop and maintain methodologies to validate silicon behavior matches pre-silicon estimates; Analyze silicon measurements (eye-diagrams, BER, BIST logs) and correlate back to design and simulation data; Chair TPIP Councils to harmonize quality criteria and test architectures across projects
Seniority
Principal, hands-on IC