Memory Subsytem Expert, MLA Technology
Core
Design, validate, and operate memory subsystems (HBM, SRAM, UCIe) for next-generation machine learning chips and servers.
Role type
Senior IC hardware engineer (memory subsystems)
Builds
High-performance machine learning silicon and servers (Trainium)
Domain
Semiconductor hardware / Machine Learning Infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
Memory subsystem design, HBM/SRAM/UCIe protocols, SERDES, silicon bring-up, validation, scripting (Python/Bash/Lua), cross-functional collaboration
Preferred skills
SOC/IO subsystems, 2.5D packaging, clocking and timing constraints, system-level debug, root-cause analysis
Technologies
HBM, SRAM, UCIe, DDR, SoC, EC2
Responsibilities
Collaborate with architects and software engineers on ML chip design; Support debug and operations of ML chips in manufacturing and data centers; Execute IP integration, packaging, and characterization; Develop scripts for functional tasks and data collection; Mentor team members on memory subsystem expertise.
Seniority
Senior, hands-on IC
