Principle DFT Engineer
Core
Define and drive DFT architecture, test strategy, and implementation for complex IPs and SoCs in networking domain products.
Role type
Principal DFT Engineer (IC)
Builds
High-speed connectivity solutions for data centers, enterprise, and cloud (ODSP, AEC, CDSP)
Domain
Semiconductor / Digital IC Design / Networking
Required skills
DFT architecture definition, Scan insertion, ATPG, MBIST, JTAG, Boundary Scan, STA, RTL/Netlist verification, Gate-level simulation, Perl/Tcl scripting, EDA tool expertise
Preferred skills
Post-Silicon bring-up, ATE debug, Silicon characterization
Technologies
Cadence, Mentor, Synopsys (Genus, Modus, NCSim/DC, Tessent, Spyglass/Tmax)
Responsibilities
Define DFT architecture and test strategy; Lead implementation of Scan, ATPG, JTAG, MBIST, and BSCAN; Execute hierarchical DFT flows; Validate production test patterns and perform gate-level simulations; Collaborate with Design, Synthesis, and Physical Design teams; Drive Post-Silicon bring-up and ATE debug.
Seniority
Principal, technical leadership & mentorship
