Sr. ASIC DFT Engineer (Silicon)
Core
Developing next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Senior IC ASIC Design for Test (DFT) Engineer
Builds
ASICs for Starlink satellites and ground infrastructure
Domain
Aerospace / Semiconductor Design for Test
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture implementation, scan insertion, compression/decompression logic, memory BIST, logic BIST, ATPG methodologies, test pattern generation, Perl/Python/Tcl/C++ scripting, Siemens Tessent tools, post-silicon bringup, ATE debug, IEEE 1500/1687 standards, low-power DFT, In-System Test (IST), boundary scan, cell-aware fault models
Preferred skills
Master's or PhD in EE/CE/Physics, extensive post-silicon bringup and failure analysis, ATE platform experience (Teradyne/Advantest), cross-functional collaboration, 7nm and below technology nodes
Technologies
Siemens Tessent, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1149.1
Responsibilities
Implement and optimize DFT architectures including scan insertion and BIST; Integrate and verify DFT IPs within subsystems; Set up and run ATPG tools for fault models and pattern compression; Create and validate DFT patterns for post-silicon bringup and ATE debug; Develop test scripts and automate processes using programming languages
Seniority
Senior, hands-on IC
