Advanced Packaging Design Verification & Physical Validation Engineer
Core
Gatekeeper of design quality for advanced packaging solutions, executing physical verification flows to catch errors before tape-out.
Role type
Senior IC physical verification engineer (advanced packaging)
Builds
Multi-die advanced packaging architectures with high-speed IP and complex power delivery networks
Domain
Semiconductor manufacturing / Advanced Packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DRC, LVS, DFM flows, TCL/Python/Perl/Scripting, multi-die architecture knowledge, foundry design rule interpretation
Preferred skills
Siemens Calibre, Synopsys IC Validator, Cadence Pegasus, 2.5D/3D IC, Chiplets, CoWoS, silicon interposers, high-density fan-out
Responsibilities
Execute comprehensive PKG floor-planning Checks, DRC, LVS, and DFM flows; Refine and optimize engineering workflows by implementing automated validation checkpoints; Identify bottlenecks and develop automated scripts or enhanced design kits; Partner with Package Architects and Supply Partners to resolve violation reports; Author engineering documentation and train team members on verification methodologies
Seniority
Senior, hands-on IC
