Staff Package Layout Engineer
Core
Define, design, and verify System-in-Package (SiP) layouts for next-generation SoCs in IoT, Automotive, and Compute spaces using 2.5D and 3D technologies.
Role type
Staff Package Layout Engineer (via careerplan.io/jobs/100461597280-staff-package-layout-engineer-at-arm)
Builds
Package designs, bump-maps, ball patterns, routing, and stack-ups for complex SoC implementations.
Domain
Semiconductor manufacturing, System-in-Package (SiP), 2.5D/3D integration
Required skills
Electrical Engineering background, 2.5D/3D package system design, SI/PI analysis, Cadence APD, Cadence Allegro, DFM/DFA optimization, design feasibility studies, team guidance
Preferred skills
EDA vendor collaboration, Python programming, SKILL scripting, TCL scripting
Technologies
Cadence APD, Cadence Allegro, Python, SKILL, TCL
Responsibilities
Define and verify package designs, optimize bump-maps and ball patterns, implement routing and stack-up creation, conduct design feasibility studies, propose layout trade-offs, define new layout methodologies
Seniority
Staff, hands-on IC with mentorship
