Staff / Principal engineer -Multi-Die Advanced Tech PPA Methodology Automation
Core
Drive sub-2nm technology PPA enablement for high-performance and low-power products by translating advanced-node capabilities into practical implementation methodologies and automation.
Role type
Staff/Principal IC physical implementation engineer (multi-die/advanced node) (via careerplan.io/jobs/100792380384-staff-principal-engineer-multi-die-advanced-tech-ppa-methodology-automation-at-arm)
Builds
End-to-end Technology-PPA solutions, scalable automation flows, and production-ready verification checks for advanced-node SoCs and multi-die systems.
Domain
Semiconductor / Advanced Silicon Design / Multi-Die Systems
Required skills
Advanced-node SoC physical implementation, Technology PPA optimization, Python/C scripting, EDA tools, Low-power design methodologies (UPF), Physical verification flows
Preferred skills
AI-assisted design automation, Advanced clocking structures, Power delivery optimization
Technologies
Python, C, Git, EDA tools, UPF, Multi-die/2.5D/3D implementation
Responsibilities
Develop scalable methodologies and automation to optimize technology-node tradeoffs; Drive cross-functional analysis of PPA limiters (congestion, IR/EM, thermal, timing); Deliver multi-die and 2.5D/3D implementation enablement; Build AI-assisted automation for PPA exploration and design closure; Convert technology learnings into repeatable flows and sign-off criteria.
Seniority
Staff/Principal, hands-on IC with strategic scope
