Analog Layout Intern
Core
Learn IC layout development, physical verification, and design rule checks for advanced CMOS technology nodes.
Role type
Analog Layout Intern
Builds
IC layouts and physical verification data for analog circuits
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence Virtuoso, Synopsys Custom Compiler, DRC/LVS, Electromigration/IR drop concepts, layout optimization, circuit element knowledge (diodes, transistors, capacitors, resistors), basic digital logic fundamentals
Preferred skills
Specialized coursework in analog design or layout, experience with 16nm to 3nm technology nodes
Technologies
Cadence Virtuoso EXL, Synopsys Custom Compiler
Responsibilities
Learn IC layout development CAD and physical verification tools, Run DRC/LVS checks, Optimize layout designs for area and parasitic R,C, Collaborate with team and present progress updates
Seniority
Intern