Design Engineer -Memory Layout
Core
Designing full-custom layouts for high-performance memory arrays and blocks in advanced process nodes to optimize power, speed, and area.
Role type
Senior IC physical design engineer (memory layout)
Builds
Custom memory layouts and verification for Arm System-on-Chip products
Domain
Semiconductor / VLSI Physical Design
Required skills
full-custom layout design, DRC/LVS/DFM verification, electro-migration and IR checks, Cadence Virtuoso, hierarchical circuit planning, PPA optimization
Preferred skills
advanced node DFM (7nm/5nm/3nm/2nm), scripting (Tcl/Perl/Shell/Skill/Scheme), circuit-design tradeoff analysis
Technologies
Cadence Virtuoso, Calibre
Responsibilities
Implement full-custom layouts from schematics to final verification, interpret physical design rules for advanced processes, verify complex memory cells, perform DRC/LVS/DFM checks, conduct electro-migration and IR reliability checks
Seniority
Mid-level, hands-on IC