Layout Engineer
Core
Develop custom standard cell layouts for Arm's sub-3nm process technology nodes, optimizing for performance, area, and power in logic libraries for next-generation SoCs.
Role type
Senior IC layout engineer (standard cells, sub-3nm)
Builds
High-performance, DRC-clean logic libraries for custom digital IPs
Domain
Semiconductor, deep submicron circuit design, advanced node physical design
Required skills
standard cell layout, physical verification (DRC/LVS), automation scripting (Python/SKILL/TCL), PPA optimization, advanced node technologies (5nm/3nm/2nm), FinFET/GAA, Cadence Virtuoso
Preferred skills
physical design implementation flow, AI tools for productivity
Technologies
Cadence Virtuoso, Calibre, Python, SKILL, TCL, PERL, LEF, GDS
Responsibilities
Design logic standard cells (inverters, flops, gates) optimized for PPA; Collaborate with circuit designers to translate schematics into layouts; Drive DRC and LVS closure using verification tools; Perform layout debugging and root-cause analysis for physical sign-off issues; Handle cell abutment, profiling, and integration constraints; Address layout-dependent effects (LDE) and double patterning/EUV compliance; Automate layout QA and regression checks using scripts; Participate in library quality audits and signoff package creation.
Seniority
Mid-level to Senior, hands-on IC