Senior Staff Digital Design Engineer
Core
Design high-performance digital ASICs for connectivity silicon powering AI data centers, focusing on high-speed datapaths, DSP pipelines, and protocol handling.
Role type
Senior Staff IC Digital ASIC Design Engineer
Builds
High-bandwidth, low-latency connectivity ASICs for Ethernet and optical interconnects
Domain
Semiconductor / Data Center Connectivity / High-Speed Networking
Deliverable
production ML models | product features
Required skills
Digital ASIC design, Micro-architecture development, SystemVerilog RTL, High-performance DSP, High-speed datapath design, Ethernet protocols, Front-end design flows (lint, CDC/RDC, synthesis, STA), Advanced process nodes (5nm/3nm), Debug skills (RTL simulation, emulation, FPGA, silicon bring-up)
Preferred skills
Advanced high-speed DSP algorithms (adaptive equalization, channel estimation), FEC architectures (LDPC, RS, BCH), PHY design experience (PMA, SerDes-adjacent logic)
Responsibilities
Define SoC-level specifications and micro-architecture for complex subsystems; Develop synthesizable SystemVerilog RTL for assigned blocks; Drive full ASIC front-end design flow including timing closure and design-for-test; Lead integration of digital logic into larger subsystems; Collaborate with DV teams on verification strategies and coverage-driven validation; Support pre-silicon validation via emulation and FPGA prototyping; Drive post-silicon bring-up and debug; Mentor junior engineers and influence technical direction
Seniority
Senior Staff, hands-on IC with significant mentorship and technical direction responsibilities
