Timing & Power Analysis CAD Engineer
Core
Develop and maintain automated timing and power signoff flows (PrimeTime-STA & PrimePower) within Marvell's M1DP CAD platform for ASIC projects.
Role type
Senior IC CAD Engineer (Timing & Power Analysis)
Builds
Automated design flows, power dashboards, and signoff reports for next-generation semiconductor chips.
Domain
Semiconductor / Physical Design / EDA
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
Synopsys PrimeTime-STA, Synopsys PrimePower, Tcl scripting, Python, hierarchical design analysis, UPF/CPF power intent, activity file annotation (FSDB/SAIF), timing variation formats (LVF/POCV/AOCV), glitch analysis, physical design flow knowledge.
Preferred skills
PrimePower RTL 2.0 adoption, glitch-aware datapath optimization, EDA vendor tool evaluation.
Technologies
Synopsys PrimeTime, Synopsys PrimePower, Tcl, Python, FSDB, VCD, SAIF, UPF, CPF, M1DP CAD platform.
Responsibilities
Develop and enhance timing/power signoff flows; generate and validate power analysis reports via dashboards; automate flow execution and debugging; interface with EDA vendors; support tapeout activities; collaborate with Physical Design and Front-End teams.
Seniority
Senior, hands-on IC
