Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
Core
Define, develop and deploy innovative STA/EMIR signoff and physical design methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes.
Role type
Senior ASIC Physical Design Methodology Engineer
Builds
Custom ML inference and training datacenter servers (AWS Inferentia, Trainium Systems)
Domain
Semiconductor hardware design / Cloud-scale Machine Learning
Deliverable
production ML models
Required skills
ASIC implementation, synthesis, STA, physical design in deep sub-micron nodes, low power design techniques, scripting (TCL, Python), EDA tool evaluation, CI/CD pipeline implementation
Preferred skills
RTL coding and debug, performance/power/area analysis and trade-offs
Technologies
AWS Inferentia, Trainium Systems, TCL, Python, EDA tools
Responsibilities
Drive optimizations in CAD flows/methodologies for Timing/EMIR signoff, PPA and TAT improvements; Interface with RTL, Physical Design, Package Design, DFT teams; Create Dashboard and Central reports for project tracking and visualizing QoR/stats; Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.
Seniority
Senior, hands-on IC