Physical Design Engineer
Core
Develop timing constraints, perform timing analysis and closure, and generate ECOs for functional and test modes at block/subsystem and SoC levels.
Role type
Senior IC physical design engineer (timing closure)
Builds
Custom SoC and CPU chip designs
Domain
Semiconductor / Electronic Design Automation (EDA)
Required skills
Timing closure at SoC and block level, STA and ECO generation tools (PrimeTime, Tempus, Tweaker), IP integration, TCL/PERL/Python scripting, data analysis
Preferred skills
Strong communication, problem-solving
Technologies
PrimeTime, Tempus, Tweaker, TCL, PERL, Python
Responsibilities
Develop and validate timing constraints for functional and test modes; Perform timing analysis and closure at block/subsystem level; Generate and track ECOs to closure with cross-functional teams
Seniority
Mid-level, hands-on IC