Senior Engineer- STA
Core
Develop and validate timing constraints and perform timing analysis/closure for functional and test modes in physical design.
Role type
Senior IC STA engineer (physical implementation)
Builds
Digital ICs (timing closure)
Domain
Semiconductor / Physical Design
Required skills
Setup/hold timing analysis, PrimeTime/Tempus, Physical Design flow (placement/CTS/routing), Timing ECO (cell sizing/buffering/Vt swaps), MMMC analysis, TCL/Perl/Python scripting, Debugging
Preferred skills
Advanced technology nodes
Responsibilities
Support timing constraints development and validation, Perform timing analysis and closure at block/subsystem level, Analyze setup and hold timing violations, Support timing ECO generation and validation, Generate and review timing reports, Support timing signoff activities
Seniority
Mid-level, hands-on IC
