Senior Principal Engineer, Design Verification
Core
Lead the development of functional verification environments, test strategies, and test plans for highly complex SoC designs using System Verilog and UVM.
Role type
Senior Principal Engineer, Design Verification
Builds
Pre-silicon validation environments and testbenches for custom silicon solutions in high-performance compute, server, network processing, and storage.
Domain
Semiconductor / SoC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and test strategies
Required skills
System Verilog, UVM methodology, random verification techniques, coverage analysis, Python scripting, Perl scripting, EDA verification tools, bug tracking, regression mechanisms, technical leadership, mentoring, cross-functional collaboration
Preferred skills
None explicitly stated as preferred, only required skills listed
Technologies
System Verilog, UVM, Python, Perl, EDA tools
Responsibilities
Develop architecture for functional verification environments including reference models and bus-functional monitors; Analyze designs to develop test strategies ensuring functional correctness; Develop verification test plans and write tests using random techniques and coverage analysis; Debug failures and resolve issues with designers; Drive development of future SoC verification methodologies; Provide leadership for a geographically dispersed verification team
Seniority
Principal, technical leadership & mentorship
