Principal Design Verification Engineer
Core
Lead verification of complex custom IP and SoC designs to deliver high-performance, efficient silicon functions.
Role type
Principal Design Verification Engineer
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, C++, Verilog, Python, Perl, random-stimulus techniques, coverage-based verification, high-speed protocols (DDR/HBM, PCIe, Ethernet), RTL debugging, simulation/emulation environments
Preferred skills
mentoring, innovation in verification methodologies
Technologies
UVM, C++, Verilog, Python, Perl, DDR, HBM, PCIe, Ethernet
Responsibilities
Own or lead verification of complex flows at SOC, subsystem, or IP levels; Plan verification strategies and test plans for complex design IP/SoC; Develop verification environments and run/debug simulations; Apply random-stimulus and coverage-based techniques to find bugs; Innovate to improve verification efficiency through methodologies or tools; Coach and mentor others in areas of expertise
Seniority
Principal, hands-on IC with mentorship
