Silicon Verification Engineer
Core
Deliver premium-quality custom IP and SoC designs by planning and executing complex verification strategies for high-performance functions.
Role type
Senior IC silicon verification engineer
Builds
Custom IP and SoC designs
Domain
Semiconductor / Computer Architecture
Deliverable
production ML models | product features
Required skills
Constrained-random verification, SystemVerilog, UVM, Formal verification (SVA), C/C++ test development, Functional coverage closure, RTL debugging, Simulation/emulation environments, Python/Perl scripting, Computer architecture knowledge
Preferred skills
Experience with processor-based testbenches, Emulation environments
Technologies
SystemVerilog, UVM, SVA, Python, Perl, Verilog
Responsibilities
Plan verification of complex design IP/SoC interacting with architecture and design engineers; Create and enhance constrained-random verification environments; Develop tests using UVM or C/C++; Analyse and debug test failures with designers; Identify and write functional coverage for stimulus and corner cases; Close coverage to meet tape out requirements.
Seniority
Senior, hands-on IC
