Senior Signal and Power Integrity Engineer
Core
Senior Signal and Power Integrity Engineer developing guidelines, reviewing, and validating high-speed SSD board designs for PCIe and DDR interfaces.
Role type
Senior IC signal and power integrity engineer (SSD)
Builds
Next-generation SSD controller hardware and flash management systems
Domain
Semiconductor / High-speed digital design
Deliverable
product features
Required skills
High-speed SSD board design, pre- and post-layout simulation, PCIe Gen 4/5/6 design, DDR4/5/LPDDR4/4x design, NVIO design, PDN design, 2D/3D electromagnetic simulation, transmission-line theory, electromagnetic field solvers, time- and frequency-domain tools, oscilloscope usage, VNA usage, TDR equipment usage, PCB design fundamentals, single-ended and differential signaling, near- and far-end crosstalk analysis, signal loss analysis, impedance control
Preferred skills
Technical leadership, eye diagram generation and interpretation at PCIe Gen x speeds, high-frequency low-loss PCB materials, high-speed flex circuit design, PCIe and DRAM operation, driver and receiver equalization schemes, IBIS knowledge, system-level compliance evaluation, PDN optimization for PSIJ analysis, PCI-SIG/JEDEC/ONFI specifications
Technologies
Sigrity, Allegro, ADS, HFSS, SIWAVE, HSPICE
Responsibilities
Mentor engineers, provide signal- and power-integrity expertise for SSD controller SoC package substrates and SSD PCB designs, develop guidelines and prepare final design reports, support PCB backend processes including stack-up definition and HDI via technologies, place components and set routing constraints, review designs, verify and validate designs in the lab, collaborate with SoC, firmware, package, and circuit design engineers, document work and communicate with design, product, and executive teams, debug issues and perform root-cause analysis
Seniority
Senior, hands-on IC
