Sr Manager Package SIPI, Annapurna Labs
Core
Lead a team of engineers to deliver Signal & Power Integrity (SI/PI) solutions for next-generation 2.5D/3D chiplet-based products, covering architecture through high-volume production.
Role type
Senior Manager, Player-Coach IC (SI/PI)
Builds
2.5D/3D IC packages (CoWoS, EMIB, 3D die stacking) for high-speed SerDes and memory interfaces
Domain
Semiconductor packaging, High-speed digital design
Required skills
SI/PI engineering, Advanced packaging (2.5D/3D), High-speed SerDes (112G+/224G PAM4), HBM3/4 design, PDN design, EDA tools (Ansys, Cadence, Keysight), Scripting (Python, MATLAB, Tcl), Team leadership
Preferred skills
PCIe Gen7/Gen6, UCIe 2.0, HBM4e, NPI, EMI/EMC, Thermal-aware SI/PI, Emerging packaging (hybrid bonding, glass substrate)
Technologies
Ansys HFSS/SIwave/Q3D, Cadence Sigrity, Keysight ADS, HSPICE/Spectre, VNA, TDR, Oscilloscope, Spectrum analyzer
Responsibilities
Lead and develop SI/PI engineering teams; Define SI/PI design methodology for 2.5D/3D packages; Drive chip-package-system co-design for HBM and PCIe; Own PDN design and sign-off; Develop channel models and perform BER/eye-diagram analysis; Establish SI/PI design guidelines and automation flows; Partner with cross-functional teams on electrical specifications; Lead post-silicon validation and model-to-hardware correlation
Seniority
Senior Manager, Player-Coach (hands-on technical leadership + team management)
