Principal Design Engineer – High-Speed Interconnect
Core
Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink) across multiple silicon products.
Role type
Principal Design Engineer (High-Speed Interconnect)
Builds
High-performance digital subsystems and silicon products
Domain
Semiconductor / High-Speed Interconnects
Required skills
SystemVerilog, PCIe, CXL, UALink, microarchitecture, RTL development, subsystem integration, AXI, CHI, ACE, APB, CDC, RDC, formal verification, synthesis, timing analysis
Preferred skills
PCIe Gen6+, CXL 2.0+, UALink, chiplets, die-to-die connectivity, RAS, IDE, TDISP, security, memory pooling, third-party IP integration
Technologies
SystemVerilog, PCIe, CXL, UALink, AXI, CHI, ACE, APB (via careerplan.io/jobs/100122542720-principal-design-engineer-high-speed-interconnect-at-arm)
Responsibilities
Translate system and protocol requirements into implementation-ready microarchitecture specifications and synthesizable RTL; Drive development from concept through RTL creation, integration, and delivery; Analyze traffic patterns and workloads to guide implementation tradeoffs; Lead technical reviews, debug cross-functional issues, and mentor engineers
Seniority
Principal, technical leadership & mentorship