Staff Signal Integrity Engineer
Core
Drive signal integrity (SI) design, simulation, optimization, and validation for next-generation AI Superchip and data center computing platforms, focusing on high-speed interconnects across silicon, packaging, and system platforms.
Role type
Staff Signal Integrity Engineer (IC)
Builds
High-speed interconnects for AI Superchips and data center platforms
Domain
Semiconductor / High-speed electronics / AI computing
Deliverable
production ML models
Required skills
High-speed signal integrity engineering, 3D electromagnetic modeling, SI simulation tools, advanced packaging knowledge, high-speed I/O signaling, transmission line analysis, SerDes technologies
Preferred skills
AI/HPC supercomputing platforms, chiplet integration, package-to-board co-design, silicon bring-up, simulation-to-measurement correlation
Technologies
Ansys HFSS, SIwave, Keysight ADS, DDR5/LPDDR, PCIe/CXL, Ethernet, SerDes
Responsibilities
Drive SI design, modeling, simulation, and validation across SoC, 2.5D/3D packaging, PCB, and system-level interconnects; Perform high-speed channel analysis and optimization for DDR5/LPDDR, PCIe/CXL, Ethernet, die-to-die, and next-generation SerDes interfaces; Develop and validate EM, S-parameter, IBIS/IBIS-AMI, and behavioral models; Lead signal integrity optimization including insertion loss, return loss, crosstalk, impedance discontinuities, equalization, and BER-based eye-margin analysis; Collaborate with silicon PHY, package, PCB, architecture, and validation teams; Support advanced packaging technologies including chiplets, interposers, high-density substrates, and heterogeneous integration
Seniority
Staff, hands-on IC
