Sr. DFT Engineer, Amazon Leo
Core
Architect and define DFT solutions for Amazon LEO chips, integrating IP and methodologies to maximize fault coverage and meet timing/power targets.
Role type
Senior IC Design for Test (DFT) Engineer
Builds
Digital system-on-chip designs for Low Earth Orbit satellite communications and Amazon gateways
Domain
Semiconductor / Aerospace & Defense / Satellite Communications
Deliverable
production ML models
Required skills
Advanced DFT techniques for deep sub-micron nodes, DFT insertion and validation automation, MBIST, JTAG controllers, RFIC collaboration, ATE pattern translation
Preferred skills
Logic BIST, mixed-signal component integration, automotive standards (single-digit DPPM), AI/ML-based automation for DFT workflows
Technologies
AI, Embedded Flow Support
Responsibilities
Architect DFT solutions tailored to LEO chip requirements, customize IP and DFT methodologies including AI-enabled flows, partner with ASIC design teams to integrate DFT logic, collaborate with RFIC teams to maximize fault coverage, work with implementation teams on timing and power targets, translate ATE patterns into tester formats, bring up digital portions of LEO chips
