Staff DFT Engineer
Core
Define and implement end-to-end DFT architecture, strategies, and flows for next-generation AI accelerators and large-scale AI SOCs.
Role type
Staff-level Design for Test (DFT) Engineer
Builds
Testable silicon for Edge AI hardware accelerators
Domain
Semiconductor design, AI hardware, Edge computing
Deliverable
production ML models | product features | infrastructure
Required skills
DFT strategy definition, Scan/MBIST/BSCAN implementation, ATPG generation, timing-annotated simulation, hierarchical DFT flows, silicon bring-up/debugging, Tcl/Python/Perl scripting
Preferred skills
Experience with Edge AI architectures, power-aware DFT, high-speed IO testing
Technologies
Siemens Tessent, Synopsys DFTMAX/TetraMAX, Cadence Genus/Modus, JTAG, IEEE 1149.1/6, IEEE 1500
Responsibilities
Define and implement complete DFT architecture including Scan, MBIST, BSCAN, and Boundary Scan; Manage DFT constraints for synthesis and STA integration; Generate high-coverage test patterns and lead verification via timing-annotated simulations; Implement advanced DFT techniques for high-bandwidth memory and low-power modes; Design and execute hierarchical DFT flows; Partner with ATE teams for silicon debugging and yield improvement
Seniority
Staff, hands-on IC with strategic autonomy
