Senior DFT Engineer
Core
Define and implement comprehensive Design-for-Test (DFT) strategies for complex digital SoC designs to ensure robust testability and quality from early design through manufacturing.
Role type
Senior IC DFT Engineer
Builds
Complex digital SoCs for 5G, IoT, and LEO satellite communications
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, scan chain insertion, ATPG pattern generation, fault simulation, MBIST/LBIST strategy, JTAG/IEEE 1149.x standards, DFT automation scripting, RTL design fundamentals
Preferred skills
3D-IC test standards, at-speed test methodologies, system-level test approaches, ATE platform familiarity, AI tools for test automation
Technologies
Synopsys DFT Compiler, Tessent, Tcl, Python, Perl, Advantest, Teradyne
Responsibilities
Define end-to-end DFT architecture, insert and verify scan chains/compression logic, own ATPG lifecycle, perform fault simulation and coverage analysis, collaborate on scan chain optimization, develop DFT automation scripts, perform DFT sign-off verification
Seniority
Senior, hands-on IC
