IP DFT Engineer
Core
Developing and implementing Design for Test (DFT) strategies for mixed-signal IP blocks to ensure high test coverage and manufactability.
Role type
Mixed-Signal IP DFT Engineer
Builds
Robust and testable mixed-signal IP solutions
Domain
Semiconductor design, mixed-signal circuits
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture development, scan insertion, test point insertion, analog test enablement, ATPG, fault simulation, coverage analysis, IP integration, DFT documentation
Preferred skills
Knowledge of industry trends in mixed-signal DFT
Technologies
ATPG, fault simulation tools, coverage analysis tools
Responsibilities
Develop and implement DFT architectures and methodologies for mixed-signal IP blocks, Collaborate with analog and digital design teams to incorporate DFT requirements, Perform DFT verification including ATPG and coverage analysis, Work with Integration DFT teams to integrate IP-level DFT features, Document DFT design, verification, and test procedures, Stay current with industry trends and best practices in mixed-signal DFT
Seniority
Mid-level IC Engineer
