Senior Engineer
Core
Senior IC physical design engineer responsible for synthesis, DFT, floorplanning, place and route, CTS, and timing/power optimization of CPU cores and system interconnects for ARM SoCs.
Role type
Senior IC physical design engineer (ASIC implementation)
Builds
Custom SoC and CPU chip designs for ARM and partners
Domain
Semiconductor / ASIC Physical Design
Required skills
ASIC implementation, Physical design, Static Timing Analysis (STA), Timing closure, Clock Tree Synthesis (CTS), Power Distribution Network (PDN) analysis, Design for Manufacturability (DFM), Physical verification, Tcl/Perl/Python scripting
Preferred skills
Low power design techniques, Verilog RTL design, ATPG tools, R/C/C++/Java/JS scripting
Technologies
Calibre, Primetime, Arm EDA tools
Responsibilities
Synthesis, DFT, Floorplan, Place and Route, CTS and Optimization of CPU cores, system interconnect and other ARM Designs; RTL-GDS closure for Hard Macro; Analyze design timing, area and power to help improve the quality of ARM Design; Analyze DRC/LVS/PERC/ERC using Calibre and perform Layout edit for Physical Verification closure; Analyze Timing using primetime and perform Timing ECO for design closure; Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP; Converting R&D concepts into real implementation solutions; Enable our partners to achieve the best possible quality of results
Seniority
Senior, hands-on IC