MLA IP Design Verification Engineer, Annapurna Labs
Core
Design and validation of machine learning hardware in data centers for cloud server platforms.
Role type
Senior IC design verification engineer (ML hardware)
Builds
ML hardware IP blocks and SoCs for AWS cloud infrastructure
Domain
Cloud computing, Machine Learning hardware, Semiconductor design
Deliverable
production ML models
Required skills
System Verilog, UVM, testbench development, multi-level logic verification (IP to SoC), debugging, stimulus generation, assertions, coverage analysis
Preferred skills
Formal verification, ARM/DSP ISAs, RF standards (4G/5G/WiMAX), Python/Perl scripting, C/C++
Technologies
System Verilog, UVM, Python, Perl, C/C++, ARM, DSP
Responsibilities
Verify/validate hardware and software solutions achieve desired functionality, develop and execute multi-faceted verification/validation plans, measure team progress towards customer metrics
Seniority
Senior, hands-on IC